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[实习招聘] 【实习】恩智浦 IC Backend Design Intern

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 楼主| 发表于 2018-1-4 17:34:07 | 显示全部楼层 |阅读模式
Ifinterested, send your CV to elena.tu@nxp.com, specifying theposition you applied.
Company Description
NXPSemiconductors enables secure connections and infrastructure for a smarterworld, advancing solutions that make lives easier, better and safer. As theworld leader in secure connectivity solutions for embedded applications, we aredriving innovation in the secure connected vehicle, end-to-end security &privacy and smart connected solutions markets.
Job Description:
-         Responsiblefor low power SOC physical design.
-         Responsiblefor die size estimation, floor-planning, power planning and power analysis.
-         Responsiblefor block level CPF design, Logic/physical synthesis, Clock tree synthesis,place and routing, STA, SI, timing closure.
-         Responsiblefor DFM, DRC/LVS physical verification.
Qualifications:
-         4thyear college student or 2nd year of post graduate student.
-         Majorin computer science, electronic engineering or equivalent.
-         Goodlanguage skill in English.
-         Basicexperience in IC physical implementation is a plus.
-         Experienceusing backend EDA tools; i.e. Cadence Virtuoso, RC, EDI, ETS, EPS, MentorGraphics Calibre etc is a plus.
-         Relevantexperience in the area of digital circuit design is a plus.
-         Goodknowledge of C/C++, Perl/TCL, scripts in Linux/Unix environment is a plus.

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