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[实习招聘] 【实习】恩智浦——IC Design类职位,上海

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 楼主| 发表于 2018-1-10 11:33:01 | 显示全部楼层 |阅读模式
【实习】恩智浦——IC Design类职位,上海
SoCDFT (Design for Test) Engineering Intern
ICBackend Design Engineering Intern
1.     SOC DFT (Design for Test)Engineering Intern
Send CV to elena.tu@nxp.com, specifying the position you’re applying to.
Responsibilities:
-       Responsible for whole chip or subsystem level DFT architecture definition and DFT planning for complex SoCdesign;
-        Perform design implementationand verification on test modules, scan insertion, test compression, MemoryBuild In Self Test, JTAG/Boundary scan.
-       Be responsible to improve thetestability of IP and chip to meet test coverage requirement.
-       Be responsible for scan patterngeneration, BIST and boundary scan pattern generation and verification.
-       Serve as the focal point for the SoCteam in interfacing with Test Engineer and Product Engineer to define the DFTrequirement, deliver test patterns and provide support on silicon test debug.
Requirements:
-       4thyear college student or 2nd year of post graduate student major inCommunications, Microelectronics Engineering and Computer Science.
-       Strong logic design and verificationbackground with good debugging capability, Experience in digital design withgood knowledge of SoC design flow, including RTL coding, simulation, synthesis,DFT and silicon test.
-       Familiar with industrial standardDFT methodology and tools, Experience on scan, ATPG, memory BIST, LBIST,T, Boundary scan, etc.
-        Analog/flash designknowledge/background will be a strong plus.
-       Knowledge in ATE  andexperience in silicon validation on tester will be plus.
-       script language like perl, tcl.will benice to have skill.
2.     IC Backend Design EngineeringIntern
SendCV to elena.tu@nxp.com, specifying the position you’re applying to.
Responsibilities:
-           Responsiblefor low power SOC physical design.
-           Responsiblefor die size estimation, floor-planning, power planning and power analysis.
-           Responsiblefor block level CPF design, Logic/physical synthesis, Clock tree synthesis,place and routing, STA, SI, timing closure.
-           Responsiblefor DFM, DRC/LVS physical verification.
Requirements:
-           4th year college student or 2nd yearof post graduate student.
-           Major in computer science, electronicengineering or equivalent.
-           Good language skill in English.
-           Basic experience in IC physicalimplementation is a plus.
-           Experience using backend EDA tools;i.e. Cadence Virtuoso, RC, EDI, ETS, EPS, Mentor Graphics Calibre etc is aplus.
-           Relevant experience in the area ofdigital circuit design is a plus.
-           Good knowledge of C/C++, Perl/TCL,scripts in Linux/Unix environment is a plus.

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